A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS

Authors: John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Eric P. Pepin, Steve Perlmutter, Visvesh Sathe, Jaques Christophe Rudell

Publication: IEEE Journal of Solid-State Circuits

Date: July 2020

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A single-chip, bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording frontend, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multichannel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. Highfrequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm 2 in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating 205 μW in recording and 142 μW in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc-dc efficiency at a maximum output power of 24 mW.

Wednesday, July 1, 2020